A continuing problem in data storage systems is the detection and correction of data errors within the storage systems. One general method for detecting single bit errors within a data word is a parity bit check. A parity bit is an extra bit included with a data word to make the number of 1's in the word (including the parity bit) either odd or even. A bit error in the word is detected by recalculating its parity and comparing the newly determined parity with the parity bit transmitted or saved with the word. An error exists if the new parity does not correspond with previously determined parity. Parity check bit schemes are limited to detecting single bit errors.
To detect multiple bit errors and correct detected errors numerous, sophisticated, Error Correction Codes (ECC) systems have been developed. One well known ECC scheme for use in disk storage systems is identified as the Reed-Solomon Cyclic Redundancy Check (R-S CRC) method. This scheme generates an error code for each data block saved to the disk storage system. Generation of Reed-Solomon ECC codes, detection of errors and the correction of detected errors may be performed by the host system CPU, thereby consuming valuable host CPU time, or by special logic external to the host. Unfortunately, most methods for generating Reed-Solomon ECC codes external to the host generate error codes in a word-serial manner, i.e. the data words within the data block being transferred to or read from must be sequentially processed through the ECC logic, thereby slowing down the rate at which data may be transferred. This word-serial manner of generating ECC codes further complicates multiple-word parallel transfers such as occur in high bandwidth disk array storage systems.